WCET 2024 – Program

22nd International Workshop on
Worst-Case Execution Time Analysis

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Keynote by Pr. Isabelle Puaut (Univ. Rennes):

Machine Learning for Timing Analysis: the good, the bad and the ugly

The microarchitecture of processors is becoming increasingly complex and less documented, making the design of timing models for WCET calculation increasingly complicated, if not impossible. We have recently experimented with the use of machine learning techniques (ML) to predict the WCET of basic blocks. Predicted WCETs can then be integrated into static WCET calculation tools, resulting in a hybrid WCET calculation. In this keynote, I will present our experience using ML for WCET calculation, across a range of architectures, from very simple ones (MSP430, Cortex M4) to more complex architectures. Rather than presenting only what worked, which fortunately allowed us to publish, I will also discuss in this keynote the bad, and even very bad, surprises encountered during the process, and how we overcame (most of) them.

(The list of accepted papers and program of the workshop will be updated soon)

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