Program

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Time	Tue, July 11	Wed, July 12	Thu, July 13	Fri, July 14
08:00-08:45	Registration	Registration	Registration
08:45-09:00		Opening
09:00-10:00	Workshop Day	Keynote – Susanne Graf Specification and Verification for MIMOS, our Framework for Design and Update of Real-Time Embedded Systems	Keynote – Hermann Kopetz Design Principles for Reducing the Complexity of Safety-Critical Embedded Systems
10:00-10:30	Workshop Day	Coffee Break	Coffee Break	Coffee Break
10:30-12:00	Workshop Day	Session 1: (Scheduling) To Schedule or not to Schedule	Session 3: (Multicore/Multiprocessor) The More, the Merrier	Session 5: (Timing analysis) Time, time time, see what’s become of me
12:00-13:30		Lunch Break	Lunch Break	Lunch Break
13:30-15:00	Workshop Day	Session 2: (Architectures and Network) Architecture should speak of its time and place, but yearn for timelessness	Session 4: (CPS) Control, control, you must learn control	Session 6: (Outstanding papers) We are the champions
15:00-15:30		Coffee Break	Coffee Break	Coffee Break
15:30-17:00	Workshop Day (till 18:00)	Real-time pitches (WiP + Journal first + Demos + …)	Industrial Challenge	Concluding Remarks and Award Ceremony (till 16:00)
Social Events	First-Timer Reception (18:00-19:00)	Poster & Demo session and reception (17:00-19:00)	Social Activity and Conference Dinner (18:00-23:00)

Keynote: Specification and Verification for MIMOS, our Framework for Design and Update of Real-Time Embedded Systems

Abstract: Traditionally, critical software in embedded real-time systems is statically verified, and once certified supposed to remain valid for the lifetime of the system itself. Modern systems, evolving in more and more open and evolving contexts impose new requirements on embedded software. MIMOS proposes a paradigm shift to respond to these challenges by means of a combination of features: (1) it is high-level and strictly model-based concerning functional and non-functional aspects to guarantee intuitive concepts to the designer whose semantics is preserved. (2) It proposes a framework for static and dynamic (monitoring-based) verification of functionality and timing completing each other. (3) Finally, our ultimate goal is allowing to ease update of critical software. The talk will give an overview on the MIMOS concepts and the tool environment for embedded and real-time systems design developed in Uppsala within Wang Yi’s ERC CUSTOMER project. Particular focus will be on the specification and verification framework that we are developing in this context.

Keynote: Design Principles for Reducing the Complexity of Safety-Critical Embedded Systems

Abstract: System Architecting deals with the decomposition of a large complex system into almost independent parts in order to reduce the implementation and validation efforts by applying the time-tested design principle divide et impera. In this presentation, we present some additional proven design principles for decomposing complex safety-critical embedded systems using the control system of a fully autonomous vehicle as an example. With the current state of the art in hardware and software, it is impossible to achieve the required safety goals of such a large complex computer system by implementing a non-fault tolerant monolithic computer architecture. We need to find a decomposition into independent Fault Containment Units (FCUs) such that a Byzantine failure of any complex FCU can be mitigated by the other correct FCUs without causing a catastrophic incident. We start by the establishment of the required safety goals and propose to make a clear distinction between the two important use cases: (i) correct behavior under well-specified nominal conditions, and (ii) safe behavior under off-nominal conditions, which cannot be fully specified in advance.

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Session 1: (Scheduling)
To Schedule or not to Schedule

• Towards Efficient Explainability of Schedulability Properties in Real-Time Systems
  Sanjoy Baruah (Washington University in St. Louis), Pontus Ekberg (Uppsala University)
• The Safe and Effective Use of Low-Assurance Predictions in Safety-Critical Systems
  Kunal Agrawal (Washington University in St. Louis), Sanjoy Baruah (Washington University in St. Louis), Michael Bender (Stony Brook University), Alberto Marchett-Spaccamela (La Sapienza Roma)
• Precise Scheduling of DAG Tasks with Dynamic Power Management
  Ashik Ahmed Bhuiyan (West Chester University), Mohammad Pivezhandi (Wayne State University), Zhishan Guo (North Carolina State University), Jing Li (New Jersey Institute of Technology), Venkata Prashant Modekurthy (University of Nevada, Las Vegas), Abusayeed Saifullah (Wayne State University)

Session 2: (Architectures and Network)
Architecture should speak of its time and place, but yearn for timelessness

• Quasi Isolation QoS Setups to Control MPSoC Contention in Integrated Software Architectures
  Sergio Garcia-Esteban (Barcelona Supercomputing Center (BSC) and Unviersitat Politecnica de Catalunya), Alejandro Serrano-Cases (Barcelona Supercomputing Center (BSC)), Enrico Mezzetti (Barcelona Supercomputing Center (BSC) and Rapita Systems S.L.), Jaume Abella (Barcelona Supercomputing Center (BSC)), Francisco J. Cazorla (Barcelona Supercomputing Center (BSC) and Rapita Systems S.L.)
• FusionClock: Energy-Optimal Clock-Tree Reconfigurations for Energy-Constrained Real-Time Systems
  Eva Dengler (Friedrich-Alexander Universität Erlangen-Nürnberg (FAU)), Phillip Raffeck (Friedrich-Alexander Universität Erlangen-Nürnberg (FAU)), Simon Schuster (Friedrich-Alexander Universität Erlangen-Nürnberg (FAU)), Peter Wägemann (Friedrich-Alexander Universität Erlangen-Nürnberg (FAU))
• Isospeed : Improving (min,+) Convolution by Exploiting (min,+)/(max,+) Isomorphism
  Raffaele Zippo (Università di Pisa), Paul Nikolaus (TU Kaiserslautern), Giovanni Stea (Università di Pisa)

Session 3: (Multicore/Multiprocessor)
The More, the Merrier

• Optimal Multiprocessor Locking Protocols under FIFO Scheduling
  Shareef Ahmed (University of North Carolina at Chapel Hill), Jim Anderson (University of North Carolina at Chapel Hill)
• A Tight Holistic Memory Latency Bound Through Coordinated Management of Memory Resources Shorouk Abdelhalim (McMaster University), Danesh Germchi (University of Waterloo), Mohammed Ismail (McMaster University), Rodolfo Pellizzoni (University of Waterloo), Mohamed Hassan (McMaster University)
• Replica-Based Scheduling of Parallel Real-Time Tasks
  Federico Aromolo (Scuola Superiore Sant’Anna – Pisa), Geoffrey Nelissen (Eindhoven University of Technology), Alessandro Biondi (Scuola Superiore Sant’Anna – Pisa)

Session 4: (CPS)
Control, control, you must learn control

• Bounding the Data-Delivery Latency of DDS Messages in Real-Time Applications
  Gerlando Sciangula (Pisa Huawei Research Center and Scuola Superiore Sant’Anna – Pisa), Daniel Casini (Scuola Superiore Sant’Anna – Pisa), Alessandro Biondi (Scuola Superiore Sant’Anna – Pisa), Claudio Scordino (Pisa Huawei Research Center), Marco Di Natale (Scuola Superiore Sant’Anna – Pisa)
• A New Perspective on Criticality: Efficient State Abstraction and Runtime Monitoring of Mixed-Criticality Real-time Control Systems
  Tim Rheinfels (FAU Erlangen-Nürnberg), Maximilian Gaukler (FAU Erlangen-Nürnberg), Peter Ulbrich (TU Dortmund)
• Consensual Resilient Control: Stateless Recovery of Stateful Controllers
  Aleksandar Matovic (SnT, University of Luxembourg), Rafal Graczyk (SnT, University of Luxembourg), Federico Lucchetti (SnT, University of Luxembourg), and Marcus Völp (SnT, University of Luxembourg)

Session 5: (Timing analysis)
Time, time time, see what’s become of me

• Scheduling and compiling rate-synchronous programs with end-to-end latency constraints
  Timothy Bourke (Inria/ENS), Vincent Bregeon (Airbus), Marc Pouzet (ENS/Inria)
• CAWET: Context-Aware Worst-Case Execution Time Estimation Using Transformers
  Abderaouf Nassim Amalou (Univ Rennes, INRIA, CNRS, IRISA, Rennes), Isabelle Puaut (Univ Rennes, INRIA, CNRS, IRISA, Rennes), Elisa Fromont (Univ. Rennes, IUF, INRIA, CNRS, IRISA, Rennes)
• Impact of transient faults on timing behavior and mitigation with near-zero WCET overhead
  Pegdwende Romaric Nikiema (Univ Rennes, INRIA, Irisa), Angeliki Kritikakou (Univ Rennes, INRIA, Irisa), Marcello Traiola (Univ Rennes, INRIA, Irisa), and Olivier Sentieys (Univ Rennes, INRIA, Irisa)

Session 6: (Outstanding papers)
We are the champions

• Memory Latency Distribution-Driven Regulation for Temporal Isolation in MPSoCs
  Ahsan Saeed (Robert Bosch GmbH), Denis Hoornaert (Technical University of Munich), Dakshina Dasari (Robert Bosch GmbH), Dirk Ziegenbein (Robert Bosch GmbH), Daniel Mueller-Gritschneder (Technical University of Munich), Ulf Schlichtmann (Technical University of Munich), Andreas Gerstlauer (The University of Texas at Austin), Renato Mancuso (Boston University)
• On the Equivalence of Maximum Reaction Time and Maximum Data Age for Cause-Effect Chains
  Mario Günzel (TU Dortmund University), Harun Teper (TU Dortmund University), Kuan-Hsun Chen (University of Twente), Georg von der Brüggen (TU Dortmund University), Jian-Jia Chen (TU Dortmund University)
• Low-overhead Online Assessment of Timely Progress as a System Commodity
  Weifan Chen (Boston University), Ivan Izhbirdeev (Boston University), Denis Hoornaert (Technical University of Munich), Shahin Roozkhosh (Boston University), Patrick Carpanedo (Boston University), Sanskriti Sharma (Boston University), Renato Mancuso (Boston University)