TimeTue, July 9Wed, July 10Thu, July 11Fri, July 12
09:00-10:00Workshop DayKeynote – Adrien Gauffriau, AirbusKeynote – Francisco J. Cazorla, BSC
10:00-10:30Coffee BreakCoffee BreakCoffee Break
10:30-12:00Workshop DaySession 1: OS and Hypervisor TechnologySession 3: Real-Time on GPUsCollaborative Session
12:00-13:30Lunch BreakLunch BreakLunch Break
13:30-15:00Workshop DaySession 2: Resource Sharing and Task DependenciesSession 4: Managing Resource-Constrained DevicesSession 5: Response Time Analysis
15:00-15:30Coffee BreakCoffee BreakCoffee Break
15:30-17:00Workshop DayReal-Time PitchesIndustrial ChallengeSession 6: Network Analysis + Concluding Remarks
Social EventsFirst-Timer ReceptionPoster & Demo Session and Reception
Social Activity and Conference Dinner

Keynote – Adrien Gauffriau, Airbus. AI in Critical Avionics: Certification and Embedded Challenges

Chair: Julien Forget, Université de Lille

Abstract: Given the future challenges for Airbus in smart automation and decarbonization, this presentation will explain how artificial intelligence will play a crucial role in our upcoming products. The keynote will then focus on the paradigm shift brought about by the design of AI-based systems, and the implications in terms of algorithms, hardware architecture, and required computational power. Especially we will propose to focus on actual standardization frameworks proposed by EASA and WG114. In the third part, we will address the need to ensure semantic preservation properties (one of the major pillars required for the certification), illustrated by our work on extending the ONNX format. 

Bio: Adrien Gauffriau is an expert in embedded artificial intelligence, currently working at Airbus. He is an alumnus of Ecole Centrale de Nantes and holds a Master’s degree in Critical Embedded Systems from Supaéro.

Adrien has a distinguished career in avionics, having developed the Flight By Wire software for the Airbus A350. He has also conducted pioneering work on the use of multi-core and many-core processors for critical systems. Presently, he supports various Airbus projects aiming to deploy onboard artificial intelligence and computer vision technologies to enhance aircraft safety and expand operational capabilities. Additionally, Adrien is actively involved in establishing new industrial standards (ARP6983, EUROCAE WG114 / SAE G34)  for the development of machine learning systems within critical avionics systems.

Keynote – Francisco Cazorla, BSC. Software Timing Verification & Validation on Modern Multi-Processor System on Chip processors (MPSoCs)

Chair: Renato Mancuso, Boston University

Abstract: We are witnessing increasing autonomy requirements in critical embedded systems (CES) a in a wide range of domains, including automotive, space, avionics, and robotics. Autonomy heavily builds on complex AI software stacks that have high computing performance requirements. MPSoCs are capable of providing the required performance levels. However, the complexity of MPSoC hardware and AI-based software poses significant challenges on functional safety and, in particular, software timing verification and validation (V&V). The source of the problem lies in the non-obvious interactions among applications in the access to MPSoC’s shared resources that can cause arbitrarily large impact on performance.

In this talk I will delve into two sets of approaches aimed to mitigate the risks associated to the increasing complexity of MPSoCs on software timing behavior. First, in terms of software-only approaches I will cover analyses, methods, and technologies that addresses some key timing V&V challenges including the generation of stressful scenarios relevant for Worst-Case Execution Time (WCET) estimation, enabling WCET estimation in the context of multi-provider software with IP restrictions, and monitoring contention among tasks.  And second, in terms of hardware solutions, I will cover strategies to extend high-performance MPSoCs with features to enable their use in safety-relevant scenarios without impacting performance including several modules for increased observability and quota control, and modules for flexible performance testing.

Bio: Francisco J. Cazorla is co-head of the CAOS (Computer Architecture – Operating System) research group at the Barcelona Supercomputing Center (BSC) that currently counts more than 50 members. Dr. Cazorla’s research interests cover hardware and software designs and associated analyses for multicore-based high-performance and high-integrity systems. On these topics Dr. Cazorla has coordinated several EU-funded research projects (PROARTIS, PROXIMA, MASTECS), projects funded by the European Space Agency, and bilateral projects between BSC and industry (e.g. Airbus, Thales, Rockwell Collins, IBM, Intel, …). Dr. Cazorla has been ERC Consolidator grant holder and in early 2020 he co-founded Maspatechnologies S.L., a spin-off from BSC focused on timing analysis for real-time multi-core systems. Maspatechnologies S.L. was sold to DANLAW Inc in November 2022. 

Session 1: OS and Hypervisor Technology

Chair: Giorgio Buttazzo, Scuola Superiore Sant’Anna

  • JuMP2start: Time-aware Stop-Start Technology for a Software-Defined Vehicle System (doi). Anam Farrukh (Boston University, USA) and Richard West (Boston University, USA)
  • The Omnivisor: A real-time static partitioning hypervisor extension for heterogeneous core virtualization over MPSoCs (doi, artifact). Daniele Ottaviano (Università degli Studi di Napoli Federico II, Italy), Francesco Ciraolo (Boston University, USA), Renato Mancuso (Boston University, USA), and Marcello Cinque (Università degli Studi di Napoli Federico II, Italy)
  • SlackCheck: a Linux kernel module to verify temporal properties of a task schedule (doi). Michele Castrovilli (University of Turin, Italy) and Enrico Bini (University of Turin, Italy)

Session 2: Resource Sharing and Task Dependencies

Chair: Mitra Nasri, Eindhoven University of Technology (TU/e)

  • Open Problem Resolved: The “Two” in Existing Multiprocessor PI-Blocking Bounds is Fundamental (Outstanding Paper) (doi). Shareef Ahmed (University of North Carolina at Chapel Hill, USA) and James H. Anderson (University of North Carolina at Chapel Hill, USA)
  • Optimizing per-Core Priorities to Minimize End-to-End Latencies (doi). Francesco Paladino (Scuola Superiore Sant’Anna, Italy), Alessandro Biondi (Scuola Superiore Sant’Anna, Italy), Enrico Bini (University of Turin, Italy), and Paolo Pazzaglia (Robert Bosch GmbH, Germany)
  • Deadline Miss Early Detection Method for DAG Tasks Considering Variable Execution Time (doi). Hayate Toba (Saitama University, Japan) and Takuya Azumi (Saitama University, Japan)

Session 3: Real-Time on GPUs

Chair: Thomas Carle, IRIT – University of Toulouse

  • Autonomy Today: Many Delay-Prone Black Boxes (Outstanding Paper) (doi, artifact). Sizhe Liu (University of North Carolina at Chapel Hill, USA), Rohan Wagle (University of North Carolina at Chapel Hill, USA), James H. Anderson (University of North Carolina at Chapel Hill, USA), Ming Yang (WeRide Corp., USA), Chi Zhang (WeRide Corp., USA), and Yunhua Li (WeRide Corp., USA)
  • Predictable GPU Sharing in Component-Based Real-Time Systems (doi, artifact). Syed W. Ali (University of North Carolina at Chapel Hill, USA), Zelin Tong (University of North Carolina at Chapel Hill, USA), Joseph Goh (University of North Carolina at Chapel Hill, USA), and James H. Anderson (University of North Carolina at Chapel Hill, USA)
  • GCAPS: GPU Context-Aware Preemptive Priority-based Scheduling for Real-Time Tasks (doi). Yidi Wang (University of California, Riverside, USA), Cong Liu (University of California, Riverside, USA), Daniel Wong (University of California, Riverside, USA), and Hyoseung Kim (University of California, Riverside, USA)

Session 4: Managing Resource-Constrained Devices

Chair: Kuan-Hsun Chen, University of Twente

  • Crêpe: Clock-Reconfiguration-Aware Preemption Control in Real-Time Systems with Devices (Outstanding Paper) (doi, artifact). Eva Dengler (Friedrich-Alexander-Universität Erlangen-Nürnberg, Germany) and Peter Wägemann (Friedrich-Alexander-Universität Erlangen-Nürnberg, Germany)
  • Shared Resource Contention in MCUs: A Reality Check and the Quest for Timeliness (doi). Daniel Oliveira (University of Minho, Portugal), Weifan Chen (Boston University, USA), Sandro Pinto (University of Minho, Portugal), and Renato Mancuso (Boston University, USA)
  • DeepTrust^RT: Confidential Deep Neural Inference Meets Real-Time! (doi) Mohammad Fakhruddin Babar (Washington State University, USA) and Monowar Hasan (Washington State University, USA)

Session 5: Response-Time Analysis

Chair: Yasmina Abdeddaïm, Gustave Eiffel University

  • Reachability-based Response-Time Analysis of Preemptive Tasks under Global Scheduling (doi). Pourya Gohari (Eindhoven University of Technology, The Netherlands), Jeroen Voeten (Eindhoven University of Technology, The Netherlands), and Mitra Nasri (Eindhoven University of Technology, The Netherlands)
  • Response time analysis for fixed-priority preemptive uniform multiprocessor systems (doi). Binqi Sun (Technical University of Munich, Germany), Tomasz Kloda (LAAS-CNRS, France), and Marco Caccamo (Technical University of Munich, Germany)
  • Tighter Worst-Case Response Time Bounds for Jitter-Based Self-Suspension Analysis (doi). Mario Günzel (TU Dortmund University, Germany), Georg von der Brüggen (TU Dortmund University, Germany), and Jian-Jia Chen (TU Dortmund University, Germany)

Session 6: Network Analysis

Chair: Rodolfo Pellizzoni, University of Waterloo

  • Analysis of TSN Time-Aware Shapers using Schedule Abstraction Graphs (doi). Srinidhi Srinivasan (Eindhoven University of Technology, The Netherlands), Geoffrey Nelissen (Eindhoven University of Technology, The Netherlands), Reinder J. Bril (Eindhoven University of Technology, The Netherlands and Mälardalen University, Sweden), and Nirvana Meratnia (Eindhoven University of Technology, The Netherlands)
  • Switching between left and right continuity in Network Calculus (doi). Damien Guidolin-Pina (RealTime-at-Work, France) and Marc Boyer (DTIS, ONERA Toulouse, France)

Collaborative Session@ECRTS

ECRTS will provide the community time, space and coffee for discussing new ideas, collaborations, joint papers or just really anything that came up during the conference so far.

We provide break-out rooms or the main lecture hall, as needed.

You can use this session in one of the following three ways:

  • ask for a discussion for the whole audience (to continue paper questions that had to be cut short) (lecture hall)
  • announce a topic you’d like to discuss for anyone may join (break-out room)
  • or arrange a meeting with colleagues on your own (break-out room)

Just let us know!

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