The challenge of profiling multi-core safety-critical embedded systems

Contributions to be presented at WATERS'19
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The challenge of profiling multi-core safety-critical embedded systems

Post by pagetti » Wed May 29, 2019

Title: The challenge of profiling multi-core safety-critical embedded systems

Authors: Sylvain Girbal and Jimmy Le Rhun

For many decades, the High Performance Computing (HPC) industry has relied for on profiling techniques for debugging and performance optimization purposes, may it be for single-core or multi-core systems.

On the other hand, the safety-critical industry, with the shift from single-core to multi-core COTS processors for time critical products such as avionics, railway or space computer subsystems is facing new challenges with a trade-off in terms of performance versus predictability.

In multi-core processors, concurrent accesses to shared hardware resources are generating inter-task or inter-application timing interference, breaking the timing isolation principles required by the qualification / certification standards associated with for such critical software. Several solutions have been proposed in the literature to control or regulate timing interference, but most of these solutions require to perform some level of profiling, or

However, regular profiling techniques relying on interrupts, multi-threading, or OS modules are usually not an option with Real Time Operating Systems (RTOS).

Additionally, to accurately quantify the maximum inter-application slowdown due to timing interference, we requires some specific co-runners stressing benchmarks dedicated at producing a preset workload on each shared hardware resources, and generate the adhoc traffic.

In this talk, we present the profiling techniques we are using to evaluate time predictability in the presence of timing interference and ensure real-time behavior of safety-critical applications:
1) METrICS, a measurement environment for multi-core time-critical systems running on top of the industry-standard PikeOS RTOS.
2) A set of Stressing Benchmarks, dedicated at generating workloads on specific hardware resources.
3) xTRACT Visualizer, a GUI allowing us to visualize and to analyze the collected information and measure timing-interference level.
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