-------------------------------------------------------------------------------- Call for Papers - WCET 2023 https://www.ecrts.org/wcet-2023/ July 11, 2023 Vienna, Austria -------------------------------------------------------------------------------- The 21st International Workshop on Worst-Case Execution Time Analysis (WCET 2023) targets the resource-consumption analysis of embedded systems in a broad sense, with an emphasis on techniques to analyze the worst-case execution time (WCET) of real-time software. The workshop covers a wide range of topics related to embedded real-time systems, timing analysis, program analysis, as well as hardware and operating-system designs. With the goal of comprehensively meeting resource requirements, the WCET Workshop 2023 welcomes contributions of analysis techniques for resources other than time, such as energy or memory. # Important Dates * Submission deadline: May 11 * Acceptance notification: May 30 * Workshop day: July 11 # Location As in previous years, the 21st edition of the WCET workshop will be co-located with the Euromicro Conference on Real-Time Systems (ECRTS 2023) in Vienna, Austria, from July 11-14, 2023. # Goals and Topics A large class of embedded systems is distinguished from general-purpose computing systems by the need to satisfy (strict) resource requirements. The analysis of such systems is challenging due to the interaction of the physical environment with the system's software, which, in turn, interacts with the underlying hardware. All these interactions make it difficult in practice to guarantee that a system meets all its resource requirements. Designers and engineers thus strive for their systems to be predictable and analyzable, thereby facilitating the verification of the systems' worst-case behavior. In order to foster vivid discussions, the workshop especially appreciates statements and approaches that are innovative or controversial. Topics of interest include, but are not limited to: * Static/measurement-based/hybrid analysis techniques * Program-flow analyses (e.g., loop bounds, infeasible paths) * Microarchitectural resource-consumption modeling * Hardware designs for predictability * Predictable, resource-aware operating systems * Analysis of resources other than time (e.g., worst-case energy consumption) * Trade-offs between resource demands * Tools for worst-case analysis * Compiler-directed worst-case optimization & analysis * Programming-language support for embedded systems * Methods & benchmarks for worst-case-analysis evaluation * Machine-learning approaches for worst-case analysis * WCET analysis in the academic curriculum * Integration of WCET & schedulability analysis * Analysis of parallel applications & many-core systems * Case studies & industrial experiences # Submission Instructions Research papers should present original research results not published or submitted for publication in other forums. Accepted papers will be published via Schloss Dagstuhl's OASIcs online proceedings series. By submitting a paper, the authors agree and confirm that: (1) Neither this paper nor a version close to it is under submission or will be submitted elsewhere before notification by WCET 2023. (2) If accepted, at least one author will register for WCET 2023 and present the paper at the workshop in person. Papers submitted for the WCET workshop must be written in English, must not exceed 10 pages, should conform with the OASIcs typesetting requirements, and must be submitted in PDF format using the WCET workshop paper submission website. The bibliography does not count towards the page limit of 10 pages. Author names, affiliations, and self-references should not be anonymized. * Submission website: https://easychair.org/my/conference?conf=wcet2023 * Template: http://www.dagstuhl.de/publikationen/oasics/anleitung-fuer-autoren/ # Program Committee * Konstantinos Bletsas, Polytechnic Institute of Porto (ISEP/IPP) * Hugues Cassé, IRIT - Université de Toulouse * Christian Dietrich, Technische Universität Hamburg * Zain A. H. Hammadeh, German Aerospace Center (DLR) * Sebastian Hahn, AbsInt Angewandte Informatik GmbH * Björn Lisper, Mälardalen University * Enrico Mezzetti, Barcelona Supercomputing Center * Isabelle Puaut, University of Rennes/IRISA * Peter Puschner, Vienna University of Technology * Jan Reineke, Saarland University * Christine Rochange, IRIT – Université de Toulouse * Martin Schoeberl, Technical University of Denmark * Peter Ulbrich, Technische Universität Dortmund # Workshop Chair * Peter Wägemann, Friedrich-Alexander-Universität Erlangen-Nürnberg # Steering Committee * Björn Lisper, Mälardalen University * Isabelle Puaut, University of Rennes I/IRISA * Jan Reineke, Saarland University