WCET 2019 – Call for papers

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The call-for-papers as txt-file is available here.

The International Workshop on Worst-Case Execution Time Analysis (WCET 2019) focuses on the analysis and design of real-time systems in a broad sense, with a particular emphasis on techniques to analyze the worst-case execution time (WCET) of real-time software. The workshop covers topics related to hard and soft real-time systems, program analysis, timing analysis, as well as (timing-predictable) hardware designs and operating systems. As in previous years, the 19th edition of the WCET workshop will be co-located with the Euromicro Conference on Real-Time Systems (ECRTS 2019) in Stuttgart, Germany, from July 9-12, 2019.

Goals and topics

A large class of embedded systems is distinguished from general-purpose computing systems by the need to satisfy timing requirements, often under resource constraints. The analysis of such real-time systems is often challenging due to the interaction of the physical environment with the system’s software, which in turn interacts with the underlying hardware as well as other software components. All these interactions make it difficult in practice to guarantee that a system meets all its timing requirements. Designers and engineers thus strive for their systems to be timing-predictable and analyzable, i.e., facilitate the verification of the system’s timing behavior.

The WCET workshop covers all aspects related to timing analysis and the design of timing-predictable systems, with a particular emphasis on worst-case execution time (WCET) analysis. Topics of interest include, but are not limited to:

  • Integration of WCET and schedulability analysis
  • Processor and hardware design for timing predictability
  • WCET analysis of multi-threaded and parallel applications
  • WCET analysis for multi/many-core systems and GPUs
  • Integration of WCET analysis in development processes
  • Timing-predictable, resource-aware operating systems
  • Program design for timing predictability
  • Flow analysis for WCET, loop bounds, infeasible paths
  • Low-level timing analysis, modeling/analysis of processor features
  • Measurement-based and hybrid WCET analysis
  • Tools for WCET analysis
  • Compiler-based optimization of worst-case timing
  • Methods and benchmarks for WCET analysis evaluation
  • Case studies and industrial experiences of WCET analysis
  • WCET analysis in the academic curriculum

Statements which are innovative, controversial, or that present new approaches are especially sought.

Paper submission

The submission link will appear in due time. The submission instructions are available here.

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