On an industrial approach for multi-core timing analysis

Contributions to be presented at WATERS'19
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On an industrial approach for multi-core timing analysis

Post by pagetti » Wed May 29, 2019

Title: On an industrial approach for multi-core timing analysis

Authors: Francisco J. Cazorla, Enrico Mezzetti, Jaume Abella (BSC); Christos Evripidou, Guillem Bernat (Rapita)

COTS multicores are becoming ubiquitous in critical domains such as automotive and avionics to support efficient and timely execution of advanced software functionalities. Fuelled by the need for higher degree of autonomous decision-making and operation, advanced software functionalities deploy increasingly complex and performance-hungry critical artificial intelligence algorithms to control the whole vehicle. At hardware level, embedded critical industries have been forced to consider multicore accelerator-based processors capable of providing huge levels of performance. The other side of the coin is that high-performance COTS multicores challenge the status quo in timing analysis, for which reason both the research community and the certification/standardization bodies are devoting notable effort to master the complexity of high-performance multicores in terms of software timing. As an example, in the avionics domain, in response to the increased use of multicore processors, the Certification Authorities Software Team (CAST) published the Position Paper CAST-32A named ‘Multi-core Processors’ (often referred to as just ‘CAST-32A’). This document identifies topics that could impact safety, performance and integrity of airborne software systems executing on multicore processors and provides objectives intended to guide the production of safe multicore avionics systems, thus extending DO-178C safety regulation. Similarly, in the automotive domain, functional safety is regulated by the ISO26262 standard, should the processor be multicore or not.

In this task we will show the joint effort by the Barcelona Supercomuting Center and Rapita Systems Ltd. to set the basis of a viable solution for Multicore Timing Analysis (MTA) to adhere to applicable standards and support documents (e.g. ISO26262, DO-178C and CAST-32A). We will show that the MTA process is a structured framework based on requirements traceability, which allows gathering concrete evidence for the quantification of interference channels and their impact on software timing. The proposed inter-disciplinary framework exploits the combined skills and tools of real-time experts (RPT) and hardware experts (BSC). Originally matured as part of a series of FP7 and H2020 EU projects, the MTA methodology has received a HiPEAC Technology Transfer Award in 2017. Currently, several pilot studies evaluating the technology are in execution with OEM/TIER companies in the automotive and avionics domains.

More in detail, we will cover the principles driving the proposed MTA approach including: adherence to standards to support traceability of verification requirements; MTA main technological building blocks as BSC’s micro-benchmark technology and Rapita’s Verification Suite; and its specific application steps along the standard ‘V’ software development process. We will also show examples of use of the MTA technology to capture real-time requirements in real high-performance multicore boards.

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