Search found 13 matches

by Nacho_S
Tue May 14, 2019
Forum: 2019 industrial challenge
Topic: Memory contention model (example)
Replies: 7
Views: 827

Re: Memory contention model (example)

Hello, thank you very much for your answer! I am currently analyzing the Jetson TX2 platform and have another question: Does anyone eventually know if the GPU of Jetson TX2 has accessible hardware performance counters and if yes, how to access them? Many thanks in advance. Best regards Hi, We have ...
by Nacho_S
Mon Apr 29, 2019
Forum: 2019 industrial challenge
Topic: Memory contention model (example)
Replies: 7
Views: 827

Re: Memory contention model (example)

Hi, the document describing the memory latency measurements states that LMBench (LAT_MEM_RD as specified in detail above) in conjuction with a custom-made program is used. I am interested in how exactly the latency is measured. Therefore, my questions are: 1) Are the measurements on the Tegra platf...
by Nacho_S
Fri Apr 12, 2019
Forum: 2019 industrial challenge
Topic: Memory contention model (example)
Replies: 7
Views: 827

Re: Memory contention model (example)

Hi, Hi I guess the baseline can be derived from the read/write latencies and the PU's frequency, but what about K and sGPU parameters? Are there any model entities these values can be derived from? I am working on an implementation and would like to make it as flexible as possible. You can find thos...
by Nacho_S
Thu Apr 04, 2019
Forum: 2019 industrial challenge
Topic: Amalthea Model of the Industrial Challenge 2019
Replies: 6
Views: 951

Re: Amalthea Model of the Industrial Challenge 2019

Hi thank you for the model! We're now trying to understand all the details. I noticed that there are pre/post-processing runnables for the tasks mapped to the GPU that feature additional ticks. My questions are: Where do those ticks come from? Those ticks come from opencv functions, for instance le...
by Nacho_S
Wed Mar 06, 2019
Forum: 2019 industrial challenge
Topic: Memory contention model (example)
Replies: 7
Views: 827

Memory contention model (example)

In the challenge we ask to derive a memory contention model when more than one CPU core and/or the GPU is accessing memory at the same time. Taking into account that: A task mapped to run on the GPU, needs offloading data that is acquired through the copy engine (GPU CE). Also, a GPU kernel can outp...
by Nacho_S
Tue Mar 05, 2019
Forum: 2019 industrial challenge
Topic: Description of the WATERS Industrial Challenge 2019
Replies: 5
Views: 1772

Re: Description of the WATERS Industrial Challenge 2019

Hi sorry for the confusion and please allow us to clarify. Data movements between CPU and GPU are performed by the GPU Copy Engine (CE). However, Copy Engine activity is initiated by the CPU. More specifically, copy commands are sent from the CPU to the GPU, and this latter one fetches the command f...
by Nacho_S
Thu Jun 01, 2017
Forum: 2017 industrial challenge
Topic: Challenge 2017 Solution #5: End-To-End Latency Characterization of Implicit and LET Communication Models
Replies: 2
Views: 2043

Re: Challenge 2017 Solution #5

Dear colleagues,

We have just updated our paper since we identify some typos.
The mathematical and formal characterization remains the same.

See you in Dubrovnik!

Nacho, Jorge, Paolo and Marko.
by Nacho_S
Wed May 24, 2017
Forum: 2017 industrial challenge
Topic: Challenge 2017 Solution #5: End-To-End Latency Characterization of Implicit and LET Communication Models
Replies: 2
Views: 2043

Re: Challenge 2017 Solution #5

Dear colleagues,

Please find attached our solution for the challenge :)

Nacho, Jorge, Paolo and Marko.
by Nacho_S
Thu May 19, 2016
Forum: Verification challenge
Topic: The FMTV'16 Challenge
Replies: 33
Views: 16352

Re: The FMTV'16 Challenge

Hello Arne, 3. Very good question. Right, arbitration is done at the memory, we assume no contention on the crossbar. Actually, we forgot to specify the split in access time between crossbar and memory. So your guess is right: take 8 cycles as transfer delay and 1 cycle for each access. So 8 cycles ...
by Nacho_S
Fri May 06, 2016
Forum: Verification challenge
Topic: The FMTV'16 Challenge
Replies: 33
Views: 16352

Re: The FMTV'16 Challenge

Thanks for the response, I got some new questions: - With regard to challenge 1: "ignoring memory accesses" means that the fetching of data in the reading/write phases takes "0" time? - With regard to challenge 2 when read/write time is not neglected: what happens if a task/runnable/core reads the s...
by Nacho_S
Wed Apr 27, 2016
Forum: Verification challenge
Topic: The FMTV'16 Challenge
Replies: 33
Views: 16352

Re: The FMTV'16 Challenge

Hi, we are still working in the challenge and we have some questions to ask you: - Are the R/W dependencies protected by some kind of semaphore or mutex? If so, what is the shared resource protocol used to arbitrate the access to shared resources (SRP, priority ceiling...)? if any is used. - Is the ...
by Nacho_S
Thu Apr 21, 2016
Forum: Verification challenge
Topic: The FMTV'16 Challenge
Replies: 33
Views: 16352

Re: The FMTV'16 Challenge

Thank you so much, we understand all better :)
by Nacho_S
Wed Apr 20, 2016
Forum: Verification challenge
Topic: The FMTV'16 Challenge
Replies: 33
Views: 16352

Re: The FMTV'16 Challenge

Thank you Arne for the response.

In regard of question 1 we would like to ask you about the possibility of having mixed types of task (i.e., both preemptive and cooperative) on the same core. What should the scheduling policy be in this case?

Best regards
Nacho