Title: NTGEN: a Network-on-Chip Traffic Generator toolkit for latency analysis
Authors:
Ermis Papastefanakis (Thales Communications and Security / Université Paris-Est, LIGM / ESIEE, France)
Laurent George (Université Paris-Est, LIGM / ESIEE, France)
Xiaoting Li (ECE Paris, France)
Ken Defossez (Thales Communications and Security, France)
Abstract: Characterizing Networks-on-Chip (NoCs)-based Systems-on-Chip (SoCs) involves running many tests in software simulated as well as in hardware emulated environments. Tests help characterizing a platform and give metrics that can concern many different aspects. Each metric provides useful information for qualitative or quantitative conclusions. In this paper, we present a new tool called NTGEN that covers all the chain of actions for characterising latency on a Field Programmable Gate Array (FPGA) NoC-based platform. The toolkit, can be used for generating traffic scenarios that can be automatically launched. It helps manipulating as well as analysing the results in order to represent them into meaningful information.
Keywords Network-on-chip, toolkit, traffic generator, NTGEN, latency.
Attached paper:Statistics: Posted by Sophie Quinton — Thu Jun 30, 2016
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