Tools and Benchmarks for Real-Time Systems

Regular contributions • Re: Evaluation of Mixed-Criticality Scheduling Algorithms using a Fair Taskset Generator

2016-11-09T09:15:14+01:00

Here is the cleaned version of the task set generator used.

mcfairgen.zip

Statistics: Posted by saravananr — Wed Nov 09, 2016

Regular contributions • Re: Evaluation of Mixed-Criticality Scheduling Algorithms using a Fair Taskset Generator

2016-07-13T08:23:51+01:00

Here is the presentation slides.

WATERS_2016_MC-FairGen_Slides.pdf

Statistics: Posted by saravananr — Wed Jul 13, 2016

Regular contributions • Re: Abstract: Code Generation of Time Critical Synchronous Programs on the Kalray MPPA Many-Core architecture

2016-07-11T14:52:25+01:00

Here are the slides of the presentation.

WATERS2016_rendu.pdf

Statistics: Posted by amaury — Mon Jul 11, 2016

Regular contributions • Model Interpretation for an AUTOSAR compliant Engine Control Function

2016-07-11T13:06:37+01:00

Title: Model Interpretation for an AUTOSAR compliant Engine Control Function

Authors:
Sakthivel Manikandan Sundharam, Nicolas Navet (University of Luxembourg, Luxemburg)
Sebastian Altmeyer (University of Amsterdam, Netherlands)

Abstract: Model-Based Development (MBD) is a common practice in the automotive industry to develop complex software, for instance, the control software for automotive engines, which are deployed on modern multi-core hardware architectures. Such an engine control system consists of different sub-systems, ranging from air system to the exhaust system. Each of these sub-systems, again, consists of software functions which are necessary to read from the sensors and write to the actuators. In this setting MBD provides indispensable means to model and implement the desired functionality, and to validate the functional, the non-functional, and in particular the real-time behavior against the requirements. Current industrial practice in model-based development completely relies on generative MBD, i.e., code generation to bridge the gap between model and implementation. An alternative approach, although not yet used in the automotive domain is model interpretation, the direct interpretation of the design models using interpretation engine running on top of the hardware. In this paper, we present a case study to investigate the applicability of model interpretation, in contrast to code generation, for the development of engine control systems. To this end, we model an engine cooling system, specifically the calculation of the engine-coolant temperature, using interpreted model based development, and discuss the benefits and low-lights compared to the existing code-generation practice.

Attached paper:

WATERS_2016_model_interpretation.pdf

MI-Engine-WATERS-2016.pdf

Statistics: Posted by Sakthivel Manikandan — Thu Jun 30, 2016

Regular contributions • NTGEN: a Network-on-Chip Traffic Generator toolkit for latency analysis

2016-06-30T17:51:28+01:00

Title: NTGEN: a Network-on-Chip Traffic Generator toolkit for latency analysis

Authors:
Ermis Papastefanakis (Thales Communications and Security / Université Paris-Est, LIGM / ESIEE, France)
Laurent George (Université Paris-Est, LIGM / ESIEE, France)
Xiaoting Li (ECE Paris, France)
Ken Defossez (Thales Communications and Security, France)

Abstract: Characterizing Networks-on-Chip (NoCs)-based Systems-on-Chip (SoCs) involves running many tests in software simulated as well as in hardware emulated environments. Tests help characterizing a platform and give metrics that can concern many different aspects. Each metric provides useful information for qualitative or quantitative conclusions. In this paper, we present a new tool called NTGEN that covers all the chain of actions for characterising latency on a Field Programmable Gate Array (FPGA) NoC-based platform. The toolkit, can be used for generating traffic scenarios that can be automatically launched. It helps manipulating as well as analysing the results in order to represent them into meaningful information.

Keywords Network-on-chip, toolkit, traffic generator, NTGEN, latency.

Attached paper:

WATERS_2016_NTGEN.pdf

Statistics: Posted by Sophie Quinton — Thu Jun 30, 2016

Regular contributions • Abstract: A Simulation Framework to Analyze the Scheduling of AVR tasks with respect to Engine Performance

2016-06-30T17:38:26+01:00

Title: A Simulation Framework to Analyze the Scheduling of AVR tasks with respect to Engine Performance

Authors:
Paolo Pazzaglia, Alessandro Biondi, Marco Di Natale and Giorgio Buttazzo (Scuola Superiore Sant’Anna, Pisa, Italy)

Abstract: We present a simulation framework, based on Simulink and an extension of the T-Res scheduling simulator tool to help provide a better characterization of the very popular problem of scheduling and analysis of Adaptive Variable Rate Tasks (AVR) in engine control. The purpose of the tool is to go beyond the simplistic model that assumes hard deadlines for all tasks and to study the impact of scheduling decisions with respect to the functional implementations of the control algorithms and the true performance of the engine.

Attached paper:

WATERS_2016_AVR_scheduling.pdf

Statistics: Posted by Sophie Quinton — Thu Jun 30, 2016

Regular contributions • Abstract: Code Generation of Time Critical Synchronous Programs on the Kalray MPPA Many-Core architecture

2016-06-30T16:22:16+01:00

Title: Code Generation of Time Critical Synchronous Programs on the Kalray MPPA Many-Core architecture

Authors:
Amaury Graillat (VERIMAG / Kalray, France)

Abstract:
Embedded software as found in aircraft, nuclear power plants and cars, is said to be critical since bugs can have hazardous consequence to human lives. A bug can be behavioral or temporal for instance a result too late is a bad result. Hence, we talk about time-critical software. The Worst-Case Response Time is the bound of this result computation. Critical codes are often generated from formal languages such as the Dataflow Synchronous Languages (SCADE, Lustre, Esterel, etc). Today the critical systems are still running on old single-core processors since theses processors are quite simple and make the computation of the WCRT easy. But, the growing demand for computational power in avionics and automotive makes the single-core processors limited. Multi-core processors offer enough computational power but are often too complex to allow computation of the
WCRT. Hence, many-core processors are promising because they offer high computational power thanks to numerous but very simple cores.

Our purpose is to parallelize and implement a Dataflow Synchronous program written in SCADE on a many-core processor. Nodes are statically scheduled on the cores to enhance temporal predictability. As the communications are in shared-memory, the solution makes the interferences as predicable as possible to allow the computation of the WCRT. We use a prototype of the SCADE compiler that allows developer to specify the nodes
of the program that must be executed in parallel. With this information, the compiler generates new blocks that communicate through data channels. A channel is composed of a data structure containing the data transferred between the blocks and special macros to write and read in this structure.

The execution platform is composed of 16 cores and a shared-memory divided into 16 banks such that access on a bank has no interference on the timing of access of another bank. According to the mapping information given by the developer, a node is executed on a core and its code stored in the corresponding memory bank. A sequencer allows several nodes to be executed sequentially one a core. Channels are implemented in a Remote Write manner, i.e., the result of a node in written in the memory banks of the destination nodes. To make the interference prediction easier for each node, two releases are defined: a release for execution, and a release to write the result.

We have implemented a code generator for the Kalray MPPA Bostan many-core SoC that takes the output of the SCADE compiler and the mapping and timing information provided by the developer, to generate C code using the Kalray low level libraries. We applied our study to ROSACE, an open source case-study of a flight controller. It is composed of an altitude controller and an environment simulator. We parallelized the altitude controller on one cluster using 5 cores. The environment simulation was located
on a second cluster communicating through the network-on-chip.

Statistics: Posted by Sophie Quinton — Thu Jun 30, 2016

Regular contributions • Dynamic criticality management with ARTEMIS

2016-06-30T16:09:59+01:00

Title: Dynamic criticality management with ARTEMIS

Authors:
Olivier CROS (LIGM / Université Paris-Est)
Geoffrey EHRMANN (LACSC)
Laurent GEORGE (LIGM / Université Paris-Est, ESIEE)

Abstract: In this work, we propose to detail the mixed-criticality integration inside our network simulator ARTEMIS. The objective here is to propose a solution to manage and simulate concrete criticality level changes inside network infrastructures, in order to focus on a network topology reconfiguration w.r.t to critical and non-critical messages evolutions. Through a transmission time computation model based on a probabilistic approach, we propose a solution to generate flowsets integrating mixed-criticality, in order to simulate the scheduling of these flowsets through different topologies.

Attached paper:

WATERS_2016_ARTEMIS.pdf

Statistics: Posted by Sophie Quinton — Thu Jun 30, 2016

Regular contributions • Evaluation of Mixed-Criticality Scheduling Algorithms using a Fair Taskset Generator

2016-06-30T15:54:00+01:00

Title: Evaluation of Mixed-Criticality Scheduling Algorithms using a Fair Taskset Generator

Authors:
Saravanan Ramanathan, Arvind Easwaran (Nanyang Technological University, Singapore)

Abstract:
The problem of scheduling mixed-criticality (MC) task systems is known to be NP-Hard, and as a consequence the performance of MC scheduling algorithms is frequently assessed using experimental evaluations based on randomly generated tasksets. It is therefore important to have a thorough understanding of all the parameters that impact the algorithms and a taskset generation procedure that is fair with respect to those parameters. Although there are a few popular taskset generators, there is no evaluation of the fairness properties of those generators. In fact, there is no existing study on identifying all the parameters that are relevant in the evaluation of MC scheduling algorithms. We address this shortcoming in this paper, and present a set of essential fairness properties for MC taskset generators. We also develop a new taskset generator and show that it satisfies those fairness properties. Finally, we evaluate the performance of multi-core MC scheduling algorithms using the generator, and provide new insights on the performance of those
algorithms with respect to several taskset parameters.

Attached paper:

WATERS_2016_MC-FairGen.pdf

Statistics: Posted by Sophie Quinton — Thu Jun 30, 2016

Regular contributions • MECHAniSer - A Timing Analysis and Synthesis Tool for Multi-Rate Effect Chains with Job-Level Dependencies

2016-06-30T15:46:22+01:00

Title: MECHAniSer - A Timing Analysis and Synthesis Tool for Multi-Rate Effect Chains with Job-Level Dependencies

Authors:
Matthias Becker, Saad Mubeen, Moris Behnam, Thomas Nolte (MRTC / Mälardalen University, Sweden)
Dakshina Dasari (Research and Technology Centre, Robert Bosch, India)

Abstract: Many industrial embedded systems have timing constraints on the data propagation through a chain of independent tasks. These tasks can execute at different periods which leads to under and oversampling of data. In such situations, understanding and validating the temporal correctness of end-to-end delays is not trivial. Many industrial areas further face distributed development where different functionalities are integrated on the same platform after the development process. The large effect of scheduling decisions on the end-to-end delays can lead to expensive redesigns of software parts due to the lack of analysis at early design stages. Job-level dependencies is one solution for this challenge and means of scheduling such systems are available. In this paper we present MECHAniSer, a tool targeting the early analysis of end-to-end delays in multi-rate cause effect chains with specified job-level dependencies. The tool further provides the possibility to synthesize job-level dependencies for a set of cause-effect chains in a way such that all end-to-end requirements are met. The usability and applicability of the tool to industrial problems is demonstrated via a case study.

Attached paper:

WATERS_2016_MECHAniSer.pdf

Statistics: Posted by Sophie Quinton — Thu Jun 30, 2016