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	<title>Tools and Benchmarks for Real-Time Systems</title>
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	<updated>2016-07-11T09:41:53+01:00</updated>

	<author><name><![CDATA[Tools and Benchmarks for Real-Time Systems]]></name></author>
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		<entry>
		<author><name><![CDATA[MatthiasBecker]]></name></author>
		<updated>2016-07-11T09:41:53+01:00</updated>

		<published>2016-07-11T09:41:53+01:00</published>
		<id>http://localhost/viewtopic.php?t=82&amp;p=140#p140</id>
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		<title type="html"><![CDATA[Schedulability and response time analysis • MECHAniSer - A Timing Analysis and Synthesis Tool for Multi-Rate Effect Chains with Job-Level Dependencies]]></title>

					<category term="Schedulability and response time analysis" scheme="http://localhost/viewforum.php?f=13" label="Schedulability and response time analysis"/>
		
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<strong class="text-strong">Tool Description</strong><br>MECHAniSer is a tool to compute end-to-end delays in cause-effect chains. In such chains, each task is independently triggered, possibly at different rates. The communication between task is based on register communication. <br><br>The current version of the tool computes the minimum and maximum data age of the cause-effect chains in the system. This is done without prior knowledge of the concrete schedule, hence the analysis can already be applied in early design phases. <br>In addition, the tool generates job-level dependencies to restrict the data propagation between tasks such that the possible end-to-end latency does not exceed the specified age constraint. <br>Both, the analysis and the synthesis of job-level dependencies are described in <a href="http://www.es.mdh.se/publications/4368-Synthesizing_Job_Level_Dependencies_for_Automotive_Multi_Rate_Effect_Chains" class="postlink">http://www.es.mdh.se/publications/4368- ... ect_Chains</a>.<br><br><br><strong class="text-strong">Distribution:</strong><br>The tool and the case study are available at: <a href="http://www.mechaniser.com" class="postlink">http://www.mechaniser.com</a><p>Statistics: Posted by <a href="http://localhost/memberlist.php?mode=viewprofile&amp;u=111">MatthiasBecker</a> — Mon Jul 11, 2016</p><hr />
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	</entry>
		<entry>
		<author><name><![CDATA[benny_akesson]]></name></author>
		<updated>2015-07-29T09:22:40+01:00</updated>

		<published>2015-07-29T09:22:40+01:00</published>
		<id>http://localhost/viewtopic.php?t=57&amp;p=60#p60</id>
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		<title type="html"><![CDATA[Schedulability and response time analysis • RTMemController - WCET and ACET Analysis Tool for Memory Transactions]]></title>

					<category term="Schedulability and response time analysis" scheme="http://localhost/viewforum.php?f=13" label="Schedulability and response time analysis"/>
		
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<strong class="text-strong">Description of the tool:</strong><br>RTMemController is an open-source tool for <em class="text-italics">evaluating the worst-case and average-case execution time of memory transactions</em>, which are executed by dynamically scheduling memory commands to DDR3 SDRAMs. The tool is based on the memory controller architecture and dynamic command scheduling algorithm proposed by Li et al. in ECRTS 2015. It uses the mathematical formalization of the algorithm, which has been shown to produce cycle-accurate timing behavior to a memory controller implementation in SystemC.<br><br>RTMemController includes two parts, a <em class="text-italics">memory trace processor</em> and a <em class="text-italics">command scheduler</em>. The former is responsible for providing a memory trace that contains the transactions executed by the memory controller. The memory trace is generated by combining a number of memory traces that are specified by the user. Each of them represents the memory trace from a requestor, e.g., a processor, a DMA controller or an accelerator, etc. The scheduler then executes the transactions by dynamically scheduling commands according to the proposed algorithm in our paper, which respects the timing constraints in the JEDEC DDR3 standard.<br><br>The memory trace processor reads the memory traces specified by the user, each of which represents a requestor that produces memory transactions. This tool uses a simple first-come first-serve (FCFS) mechanism. As a result, the memory trace processor combines the specified traces into a single combined trace according to the time stamps of the transactions. The generated memory trace provides a list of transactions that are executed by the memory controller. For users’ preferring arbitration policies for transactions from different requestors, it is easy to replace this memory trace processor with their own traces.<br><br>The command scheduler executes each transaction by dynamically scheduling memory commands subject to relevant DDR3 timing constraints. The scheduler <em class="text-italics">collects the actual execution time of each transaction</em> based on the command scheduling results. The <em class="text-italics">maximum execution time of a transaction with particular size is collected</em> as the measured WCET. Moreover, <em class="text-italics">the worst-case execution time (WCET) of a transaction is given by two methods</em>. <br><br><strong class="text-strong">Key uses for this tool:</strong><br>- Determine the actual and worst-case execution time of a trace that accesses a DDR3 memory.<br>- Determine the WCET of a memory transaction with a given size in a DDR3 memory.<br><br><strong class="text-strong">People:</strong><br>- Yonghui Li (Eindhoven University of Technology)<br>- Benny Akesson (CISTER/INESC TEC and ISEP, formerly CTU Prague)<br>- Kees Goossens (Eindhoven University of Technology)<br><br><strong class="text-strong">Links:</strong><br>- Website: <a href="http://www.es.ele.tue.nl/rtmemcontroller/" class="postlink">http://www.es.ele.tue.nl/rtmemcontroller/</a><br><br><strong class="text-strong">Release history:</strong><br>- v1.2 was released on Jan. 21, 2015. The result folder is automatically created, such that users can easily find the results of worst-case and average-case execution times.<br>- v1.1 was released on Oct. 29, 2014. A memory bug was fixed based on the feedback from Danlu Guo who is working at the University of Waterloo. The feedback is appreciated! <br>- v1.0 was released on May. 8, 2014. This was the first public release of the tool.<p>Statistics: Posted by <a href="http://localhost/memberlist.php?mode=viewprofile&amp;u=113">benny_akesson</a> — Wed Jul 29, 2015</p><hr />
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	</entry>
		<entry>
		<author><name><![CDATA[saad.mubeen]]></name></author>
		<updated>2015-07-07T10:48:21+01:00</updated>

		<published>2015-07-07T10:48:21+01:00</published>
		<id>http://localhost/viewtopic.php?t=49&amp;p=48#p48</id>
		<link href="http://localhost/viewtopic.php?t=49&amp;p=48#p48"/>
		<title type="html"><![CDATA[Schedulability and response time analysis • MPS-CAN Analyzer: A tool for end-to-end delay analysis of heterogeneous automotive networks]]></title>

					<category term="Schedulability and response time analysis" scheme="http://localhost/viewforum.php?f=13" label="Schedulability and response time analysis"/>
		
		<content type="html" xml:base="http://localhost/viewtopic.php?t=49&amp;p=48#p48"><![CDATA[
<strong class="text-strong">Tool Description</strong><br>MPS-CAN Analyzer is a response time analyzer for Mixed Periodic and Sporadic messages in Controller Area Network (CAN). It implements a number of response-time analyses for CAN addressing various queueing policies, buffer limitations in the CAN controllers, and various transmission modes implemented by higher-level protocols for CAN. It also integrates the response-time analysis for Ethernet AVB and CAN-to-Ethernet AVB Gateway. Hence, the tool is able to calculate the end-to-end delays of global messages that are originated in CAN network and are traversed through the gateway to the AVB network. <br><br><strong class="text-strong">Distribution:</strong><br>The tool and several test cases are available at: <a href="https://github.com/saadmubeen/MPS-CAN" class="postlink">https://github.com/saadmubeen/MPS-CAN</a><p>Statistics: Posted by <a href="http://localhost/memberlist.php?mode=viewprofile&amp;u=91">saad.mubeen</a> — Tue Jul 07, 2015</p><hr />
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	</entry>
		<entry>
		<author><name><![CDATA[ggiannopoulou]]></name></author>
		<updated>2015-06-24T16:12:07+01:00</updated>

		<published>2015-06-24T16:12:07+01:00</published>
		<id>http://localhost/viewtopic.php?t=21&amp;p=19#p19</id>
		<link href="http://localhost/viewtopic.php?t=21&amp;p=19#p19"/>
		<title type="html"><![CDATA[Schedulability and response time analysis • RTC: Real-Time Calculus Toolbox]]></title>

					<category term="Schedulability and response time analysis" scheme="http://localhost/viewforum.php?f=13" label="Schedulability and response time analysis"/>
		
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<strong class="text-strong">Description of the tool</strong><br>The Real-Time Calculus (RTC) Toolbox is a free Matlab toolbox for system-level performance analysis of distributed real-time and embedded systems.<br>The RTC Toolbox is based on an efficient representation of Variability Characterization Curves (VCC's) and implements most min-plus and max-plus algebra operators for these curves. On top of the min-plus and max-plus algebra operators, the RTC Toolbox provides a library of functions for Modular Performance Analysis with Real-Time Calculus.<br><br><strong class="text-strong">Usage scope</strong><br>To be defined<br><br><strong class="text-strong">People</strong><br>- Ernesto Wandeler<br>- Lothar Thiele<br><br><strong class="text-strong">Links</strong><br>- Website: <a href="http://www.mpa.ethz.ch/Rtctoolbox" class="postlink">website</a><br><br><strong class="text-strong">Work in progress</strong><br>2015.06.30 - To be defined<br><br>Release history<br>2011.03.07 - Tutorial extended.<br>2011.01.31 - Extensions to analyze multicore systems.<br>2010.07.26 - Interface to SymTA/S analysis tool.<br>2010.07.26 - Extensions for structured event streams.<br>2009.01.30 - BugFix and Update released.<br>2008.12.23 - Beta Version 1.2 released.<br>2008.10.14 - BugFix released.<br>2008.07.16 - BugFix released.<br>2008.05.30 - BugFix released.<br>2008.02.06 - BugFix released.<br>2007.09.24 - New components and tutorial.<br>2007.07.05 - BugFix released.<br>2007.06.25 - BugFix released.<br>2007.06.21 - New Version released.<br>2007.03.21 - BugFix released.<br>2006.10.02 - New tutorials and Java API released.<br>2006.10.02 - BugFix released.<br>2006.04.04 - First tutorial published.<br>2006.02.27 - First official beta version released.<p>Statistics: Posted by <a href="http://localhost/memberlist.php?mode=viewprofile&amp;u=77">ggiannopoulou</a> — Wed Jun 24, 2015</p><hr />
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	</entry>
		<entry>
		<author><name><![CDATA[medinajl]]></name></author>
		<updated>2015-06-24T11:22:09+01:00</updated>

		<published>2015-06-24T11:22:09+01:00</published>
		<id>http://localhost/viewtopic.php?t=12&amp;p=12#p12</id>
		<link href="http://localhost/viewtopic.php?t=12&amp;p=12#p12"/>
		<title type="html"><![CDATA[Schedulability and response time analysis • MAST: Modeling and Analysis Suite for Real-Time Applications]]></title>

					<category term="Schedulability and response time analysis" scheme="http://localhost/viewforum.php?f=13" label="Schedulability and response time analysis"/>
		
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<strong class="text-strong">Description of the tool</strong><br>MAST is an open-source suite of tools to perform schedulability analysis of real-time distributed systems that assesses a rich variety of timing requirements. Via sensitivity analysis, you will know how far or close the system is from meeting those requirements. MAST uses a versatile and composable input model for the real-time behavior of the modules and platforms that form your system.<br><br><strong class="text-strong">Usage scope</strong><br>To be defined<br><br><strong class="text-strong">People</strong><br>- Michael González Harbour (Universidad de Cantabria)<br><br><strong class="text-strong">Links</strong><br>- Website: <a href="http://mast.unican.es/" class="postlink">http://mast.unican.es/</a><br><br><strong class="text-strong">Work in progress</strong><br>2015.06.30 - To be defined<br><br>Release history<br>2015.06.30 - To be defined<p>Statistics: Posted by <a href="http://localhost/memberlist.php?mode=viewprofile&amp;u=61">medinajl</a> — Wed Jun 24, 2015</p><hr />
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	</entry>
		<entry>
		<author><name><![CDATA[jschlatow]]></name></author>
		<updated>2015-06-23T14:03:12+01:00</updated>

		<published>2015-06-23T14:03:12+01:00</published>
		<id>http://localhost/viewtopic.php?t=5&amp;p=5#p5</id>
		<link href="http://localhost/viewtopic.php?t=5&amp;p=5#p5"/>
		<title type="html"><![CDATA[Schedulability and response time analysis • pyCPA: a pragmatic Python implementation of Compositional Performance Analysis]]></title>

					<category term="Schedulability and response time analysis" scheme="http://localhost/viewforum.php?f=13" label="Schedulability and response time analysis"/>
		
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<strong class="text-strong">Description of the tool</strong><br>Given, you have a (distributed) real-time system and you want to know about worst-case (end-to-end) timing behavior, then you can use pyCPA to obtain these bounds.<br><br>You provide your architecture in the form of resources such as busses and CPUs and the corresponding scheduling policies. In a second step, you define your task-graph which is a specification of task-communication (precedence relations) and tasks' properties (best/worst-case execution times, activation patterns).<br><br>pyCPA will then calculate the following metrics:<br><ul><li> worst-case response times (wcrt) of tasks</li><li> end-to-end timing of task chains</li><li> backlog of task activations (maximum buffer sizes)</li><li> output event models of dependent tasks</li></ul><strong class="text-strong">Usage scope</strong><br>pyCPA is a pragmatic Python implementation of Compositional Performance Analysis (aka the SymTA/S approach provided by Symtavision) used for research in worst-case timing analysis. Unlike the commercial SymTA/S tool, pyCPA is not intended for commercial-grade use and does not guarantee correctness of the implementation.<br><br>The aim of pyCPA is also to provide an analysis core that can be easily extended (e.g. schedulers, activation patterns, etc.).<br><br><strong class="text-strong">People</strong><br>- Philip Axer (TU Braunschweig, NXP)<br>- Jonas Diemer (TU Braunschweig, Symtavision)<br>- Daniel Thiele (TU Braunschweig)<br>- Johannes Schlatow (TU Braunschweig)<br><br><strong class="text-strong">Links</strong><br>- Website: <a href="http://pycpa.readthedocs.org" class="postlink">http://pycpa.readthedocs.org</a><br>- Code: <a href="https://bitbucket.org/pycpa/pycpa/overview" class="postlink">bitbucket repository</a><br><br><strong class="text-strong">Release history</strong><br>Continuous release and improvement of the core.<p>Statistics: Posted by <a href="http://localhost/memberlist.php?mode=viewprofile&amp;u=78">jschlatow</a> — Tue Jun 23, 2015</p><hr />
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