RTMemController - WCET and ACET Analysis Tool for Memory Transactions

Tools for schedulability analysis, response-time analysis and related issues
E.g.: scheduler synthesis, bounds on maximum response times, end-to-end latencies, buffer sizes...
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RTMemController - WCET and ACET Analysis Tool for Memory Transactions

Post by benny_akesson » Wed Jul 29, 2015

Description of the tool:
RTMemController is an open-source tool for evaluating the worst-case and average-case execution time of memory transactions, which are executed by dynamically scheduling memory commands to DDR3 SDRAMs. The tool is based on the memory controller architecture and dynamic command scheduling algorithm proposed by Li et al. in ECRTS 2015. It uses the mathematical formalization of the algorithm, which has been shown to produce cycle-accurate timing behavior to a memory controller implementation in SystemC.

RTMemController includes two parts, a memory trace processor and a command scheduler. The former is responsible for providing a memory trace that contains the transactions executed by the memory controller. The memory trace is generated by combining a number of memory traces that are specified by the user. Each of them represents the memory trace from a requestor, e.g., a processor, a DMA controller or an accelerator, etc. The scheduler then executes the transactions by dynamically scheduling commands according to the proposed algorithm in our paper, which respects the timing constraints in the JEDEC DDR3 standard.

The memory trace processor reads the memory traces specified by the user, each of which represents a requestor that produces memory transactions. This tool uses a simple first-come first-serve (FCFS) mechanism. As a result, the memory trace processor combines the specified traces into a single combined trace according to the time stamps of the transactions. The generated memory trace provides a list of transactions that are executed by the memory controller. For users’ preferring arbitration policies for transactions from different requestors, it is easy to replace this memory trace processor with their own traces.

The command scheduler executes each transaction by dynamically scheduling memory commands subject to relevant DDR3 timing constraints. The scheduler collects the actual execution time of each transaction based on the command scheduling results. The maximum execution time of a transaction with particular size is collected as the measured WCET. Moreover, the worst-case execution time (WCET) of a transaction is given by two methods.

Key uses for this tool:
- Determine the actual and worst-case execution time of a trace that accesses a DDR3 memory.
- Determine the WCET of a memory transaction with a given size in a DDR3 memory.

- Yonghui Li (Eindhoven University of Technology)
- Benny Akesson (CISTER/INESC TEC and ISEP, formerly CTU Prague)
- Kees Goossens (Eindhoven University of Technology)

- Website: http://www.es.ele.tue.nl/rtmemcontroller/

Release history:
- v1.2 was released on Jan. 21, 2015. The result folder is automatically created, such that users can easily find the results of worst-case and average-case execution times.
- v1.1 was released on Oct. 29, 2014. A memory bug was fixed based on the feedback from Danlu Guo who is working at the University of Waterloo. The feedback is appreciated!
- v1.0 was released on May. 8, 2014. This was the first public release of the tool.
Dr. Benny Akesson
Research Associate
Polytechnic Institute of Porto


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