Modeling Accesses to Shared Memories in Multi-Processor Systems-on-Chip (MPSoCs)

Contributions to be presented at WATERS'18
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pagetti
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Modeling Accesses to Shared Memories in Multi-Processor Systems-on-Chip (MPSoCs)

Post by pagetti » Wed May 23, 2018

Title: Modeling Accesses to Shared Memories in Multi-Processor Systems-on-Chip (MPSoCs)

Authors: Adam Kostrzewa, Selma Saidi and Rolf Ernst

Abstract:
Multi-Processor Systems-on-Chip (MPSoCs) enable high performance through integration and concurrent execution of previously separated applications and functions. However, due to an extensive sharing of hardware components, the prediction of the timing behavior in such systems becomes complicated. Even in setups with static task-to-processor mapping, the real-time analysis of accesses to shared memories is non-trivial as it includes the acquisition of several system resources, e.g., interconnect and controllers, and a broad spectrum of possible interference.
In this talk, we discuss how to apply the Compositional Performance Analysis framework to model these new dependencies and bound the worst-case latencies in a shared memory system efficiently. We show that careful management of data storage and transfers in the MPSoC is critical for achieving the performance and safety. Furthermore, we present how effects of locality of accesses and their granularity influence the response time and introduce dynamic hardware effects which must be covered by the analysis.
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